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8-mbit (512k x 16) static ram cy62157ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05445 rev. *e revised may 07, 2007 features ? tsop i package configurable as 512k x 16 or as 1m x 8 sram ? high speed: 45 ns ? wide voltage range: 2.20v?3.60v ? pin compatible with cy62157dv30 ? ultra low standby power ? typical standby current: 2 a ? maximum standby current: 8 a (industrial) ? ultra low active power ? typical active current: 1.8 ma @ f = 1 mhz ? easy memory expansion with ce 1 , ce 2 , and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in both pb-free and non pb-free 48-ball vfbga, pb-free 44-pin tsop ii and 48-pin tsop i packages functional description [1] the cy62157ev30 is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input or output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce 1 high or ce 2 low) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) ? write operation is active (ce 1 low, ce 2 high and we low) to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 10 for a complete description of read and write modes. logic block diagram 512k 16 / 1m x 8 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power down circuit bhe ble ce 2 ce 1 ce 2 ce 1 byte notes 1. for best practice recommendations, plea se refer to the cypress application note an1064, sram system guidelines .
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 2 of 14 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( a) f = 1mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62157ev30ll ind?l/auto-a 2.2v 3.0 3.6 45 1.8 3 18 25 2 8 pin configuration the following pictures show the 44-pin tsop ii and 48-pin tsop i pinouts. [3, 4, 5] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 18 17 20 19 27 28 25 26 22 21 23 24 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 nc dnu we ce2 dnu bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss io15/a19 io7 io14 io6 io13 io5 io12 io4 vcc io11 io3 io10 io2 io9 io1 io8 io0 oe vss ce1 a0 a 5 44-pin tsop ii top view a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 17 a 18 a 9 a 10 a 11 a 12 a 15 a 16 a 14 a 13 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss a 8 48-pin tsop i (512k x 16 / 1m x 8) top view notes 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. 3. nc pins are not connected on the die. 4. the 44-tsop ii package has only one chip enable (ce ) pin. 5. the byte pin in the 48-tsop i package has to be tied high to use the device as a 512k 16 sram. the 48-tsop i package can also be used as a 1m 8 sram by tying the byte signal low. in the 1m x 8 configuration, pin 45 is a19, while bhe , ble and io8 to io14 pins are not used (dnu).
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 3 of 14 the following picture shows the 48-ball vfbga pinout. [3, 4, 5] pin configuration (continued) we v cc a 11 a 10 nc a 6 a 0 a 3 ce 1 io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe v ss a 7 io 0 bhe ce 2 a 2 a 1 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 a 17 48-ball vfbga top view
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 4 of 14 maximum ratings exceeding maximum ratings may sh orten the battery life of the device. user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potential ................................?0.3v to 3.9v (v ccmax + 0.3v) dc voltage applied to outputs in high-z state [6, 7] ................?0.3v to 3.9v (v ccmax + 0.3v) dc input voltage [6, 7] ........... ?0.3v to 3.9v (v cc max + 0.3v) output current into outputs (low) ............................ 20 ma static discharge voltage ........ .............. .............. ...... > 2001v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [8] cy62157ev30ll ind?l/auto-a ?40c to +85c 2.20v to 3.60v electrical characteristics over the operating range parameter description test conditions 45 ns (ind ?l/auto-a) unit min typ [2] max v oh output high voltage i oh = ?0.1 ma 2.0 v i oh = ?1.0 ma, v cc > 2.70v 2.4 v v ol output low voltage i ol = 0.1 ma 0.4 v i ol = 2.1ma, v cc > 2.70v 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3 v v cc = 2.7v to 3.6v 2.2 v cc + 0.3 v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 18 25 ma f = 1 mhz 1.8 3 i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60v 28 a i sb2 [9] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 28 a capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 6. v il(min) = ?2.0v for pulse durations less than 20 ns. 7. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 8. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 9. only chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte (48 tsop i only) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 10. tested initially and after any design or proce ss changes that may affect these parameters.
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 5 of 14 thermal resistance [10] parameter description test conditions bga tsop i tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 72 74.88 76.88 c/w jc thermal resistance (junction to case) 8.86 8.6 13.52 c/w ac test loads and waveforms figure 1. ac test loads and waveforms parameters 2.5v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th data retention characteristics over the operating range parameter description conditions min typ [2] max unit v dr v cc for data retention 1.5 v i ccdr [9] data retention current v cc = 1.5v, ce 1 > v cc ? 0.2v, ce 2 < 0.2v , v in > v cc ? 0.2v or v in < 0.2v ind?l/auto-a 2 5 a t cdr [10] chip deselect to data retention time 0ns t r [11] operation recovery time t rc ns data retention waveform [12] figure 2. data retention waveform v cc(min) t cdr v dr > 1.5v data retention mode t r v cc(min) ce 1 or v cc bhe .ble ce 2 or notes 11. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 12. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble .
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 6 of 14 switching characteristics over the operating range [13, 14] parameter description 45 ns (ind?l/auto-a) unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low-z [15] 5ns t hzoe oe high to high-z [15, 16] 18 ns t lzce ce 1 low and ce 2 high to low-z [15] 10 ns t hzce ce 1 high and ce 2 low to high-z [15, 16] 18 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high and ce 2 low to power down 45 ns t dbe ble /bhe low to data valid 45 ns t lzbe ble /bhe low to low-z [15, 17] 5ns t hzbe ble /bhe high to high-z [15, 16] 18 ns write cycle [18] t wc write cycle time 45 ns t sce ce 1 low and ce 2 high to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [15, 16] 18 ns t lzwe we high to low-z [15] 10 ns notes 13. test conditions for all parameters other than tri-state paramet ers assume signal transition time of 3 ns or less, timing ref erence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 5 . 14. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 17. if both byte enables are toggl ed together, this value is 10 ns. 18. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 7 of 14 switching waveforms read cycle no. 1 (address transition controlled) [19, 20] figure 3. read cycle no. 1 read cycle no. 2 (oe controlled) [20, 21] figure 4. read cycle no. 2 previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 19. the device is continuously selected. oe , ce 1 = v il , bhe , ble , or both = v il , and ce 2 = v ih . 20. we is high for read cycle. 21. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 8 of 14 write cycle no. 1 (we controlled) [18, 22, 23] figure 5. write cycle no. 1 write cycle no. 2 (ce 1 or ce 2 controlled) [18, 22, 23] figure 6. write cycle no. 1 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 24 ce 1 address ce 2 we data io oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 24 ce 1 address ce 2 we data io oe bhe /ble notes 22. data io is high impedance if oe = v ih . 23. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 24. during this period, the ios are in output state. do not apply input signals.
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 9 of 14 write cycle no. 3 (we controlled, oe low) [23] figure 7. write cycle no. 3 write cycle no. 4 (bhe /ble controlled, oe low) [23] figure 8. write cycle no. 4 switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 24 ce 1 address ce 2 we data io bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 24 ce 1 address ce 2 we data io bhe /ble
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 10 of 14 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high-z deselect/power down standby (i sb ) x l x x x x high-z deselect/power down standby (i sb ) x x x x h h high-z deselect/power down standby (i sb ) l h h l l l data out (io 0 ?io 15 ) read active (i cc ) l h h l h l data out (io 0 ?io 7 ); high-z (io 8 ?io 15 ) read active (i cc ) l h h l l h high-z (io 0 ?io 7 ); data out (io 8 ?io 15 ) read active (i cc ) l h h h l h high-z output disabled active (i cc ) l h h h h l high-z output disabled active (i cc ) l h h h l l high-z output disabled active (i cc ) l h l x l l data in (io 0 ?io 15 ) write active (i cc ) l h l x h l data in (io 0 ?io 7 ); high-z (io 8 ?io 15 ) write active (i cc ) l h l x l h high-z (io 0 ?io 7 ); data in (io 8 ?io 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62157ev30ll-45bvi 51-85150 48-ball very fine pitch ball grid array industrial cy62157ev30ll-45bvxi 51-85150 48-ball very fine pitch ball grid array (pb-free) cy62157ev30ll-45zsxi 51-85087 44-pin thin small outline package type ii (pb-free) CY62157EV30LL-45ZXI 51-85183 48-pin thin small outline package type i (pb-free) 45 cy62157ev30ll-45bvxa 51-85150 48-ball very fine pitch ball grid array (pb-free) automotive-a cy62157ev30ll-45zsxa 51-85087 44-pin thin small outline package type ii (pb-free) contact your local cypress sales represen tative for availability of these parts.
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 11 of 14 package diagrams figure 9. 48-pin vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 12 of 14 figure 10. 44-pin tsop ii, 51-85087 package diagrams (continued) 51-85087-*a
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 13 of 14 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 11. 48-pin tsop i (12 mm x 18.4 mm x 1.0 mm), 51-85183 mobl is a registered trademark, and more battery life is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 1 n 0.020[0.50] 0.007[0.17] 0.037[0.95] 0.002[0.05] 0-5 max. 0.028[0.70] 0.010[0.25] 0.004[0.10] 0.011[0.27] 0.041[1.05] 0.047[1.20] 0.472[12.00] 0.724 [18.40] 0.787[20.00] 0.006[0.15] typ. 0.020[0.50] 0.008[0.21] gauge plane seating plane 0.004[0.10] dimensions in inches[mm] min. max. jedec # mo-142 51-85183-*a
cy62157ev30 mobl ? document #: 38-05445 rev. *e page 14 of 14 document history page document title: cy62157ev30 mobl ? , 8-mbit (512k x 16) static ram document number: 38-05445 rev. ecn no. issue date orig. of change description of change ** 202940 see ecn aju new data sheet *a 291272 see ecn syt converted from advance information to preliminary removed 48-tsop i package and the associated footnote added footnote stating 44 tsop ii package has only one ce on page # 2 changed v cc stabilization time in footnote #7 from 100 s to 200 s changed i ccdr from 4 to 4.5 a changed t oha from 6 to 10 ns for both 35 and 45 ns speed bins changed t doe from 15 to 18 ns for 35 ns speed bin changed t hzoe , t hzbe and t hzwe from 12 and 15 ns to 15 and 18 ns for 35 and 45 ns speed bins respectively changed t hzce from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns speed bins respectively changed t sce , t aw and t bw from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns speed bins respectively changed t sd from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns speed bins respectively added lead-free package information *b 444306 see ecn nxr converted from preliminary to final. changed ball e3 from dnu to nc removed redundant footnote on dnu. removed 35 ns speed bin removed ?l? bin added 48 pin tsop i package added automotive product information. changed the i cc typ value from 16 ma to 18 ma and i cc max value from 28 ma to 25 ma for test condition f = fax = 1/t rc. changed the i cc max value from 2.3 ma to 3 ma for test condition f = 1mhz. changed the i sb1 and i sb2 max value from 4.5 a to 8 a and typ value from 0.9 a to 2 a respectively. modified isb 1 test condition to include bhe , ble updated thermal resistance table. changed test load capacitance from 50 pf to 30 pf. added typ value for i ccdr . changed the i ccdr max value from 4.5 a to 5 a corrected t r in data retention characteristics from 100 s to t rc ns. changed t lzoe from 3 to 5 changed t lzce from 6 to 10 changed t hzce from 22 to 18 changed t lzbe from 6 to 5 changed t pwe from 30 to 35 changed t sd from 22 to 25 changed t lzwe from 6 to 10 added footnote #15 updated the ordering information and replaced the package name column with package diagram. *c 467052 see ecn nxr modified data sheet to include x8 configurability. updated the ordering information table *d 925501 see ecn vkn removed automotive-e information added preliminary automotive-a information added footnote #10 related to i sb2 and i ccdr added footnote #15 related ac timing parameters *e 1045801 see ecn vkn converted automotive-a specs from preliminary to final updated footnote #9

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